Machine Learning Engineers: We're looking for software engineers with a machine learning background or architects with strong software skills to develop our ML library that maps from TensorFlow/Caffe2/Torch/Theano/etc to our machine learning chip, efficiently mapping the high level tensor operations to our target RISC-V hardware. Areas of work include the layer compiler, the memory allocator and optimizer, the templated layer libraries and the runtime environment running on our platform.
3D Driver Engineers: We're looking for software engineers with a strong background and deep understanding of 3D algorithms and techniques to help us build our DX12 and Vulkan 3D drivers. Areas of work cover the full spectrum of the driver: from the top level optimization layers to driving our RISC-V hardware through the PCIe interface. There is also a runtime layer running on the RISC-V hardware that distributes and load-balances all the primitive work to the RISC-V engines.
PCie Device Driver Engineers: We're looking for driver engineers with a proven track record of bringing up a PCIe driver for the Windows and Linux environments.
RTL/Microarchitecture Engineers: We’re looking for individuals with either a strong RTL or a strong architecture/microarchitecture background interested in working in several areas of a RISC-V design for an advanced technology node. In particular, areas of focus will be the processor pipeline, d-cache, i-cache, the l2-pipeline and a custom memory controller. We believe in very “vertical” engineers that fully understand the problem to be solved and can take it down to RTL level. We’re proud of not using C/C++ simulators and instead being able to test our ideas directly in Verilog, from which we can get IPC, Frequency, Area and Power!
Verification Engineers: We're looking for individuals with either a strong Verification or strong microarchitecture background interested in working in the verification of a RISC-V design for and advanced technology node. Areas of focus are the vector instructions, the risc-v base ISA, the risc-v privileged ISA, cache coherency protocols, inter-processor communication protocols and full SoC verification.
Back-End Engineers: We're looking for individuals with experience in synthesis, place & route flows and floorplaning and wireplanning. Experience in clock tree synthesis and/or custom clock trees is also very welcome. Experience in netlist power analysis tools (such as PrimeTime/PX) will also be key in these positions. You'll be helping in floorplanning in a very advanced technology node, creating the synthesis and place& route flow, integrating several custom blocks and running the resulting p&r netlists though power analysis tools.
Location: All these positions are for our Barcelona office. For extraordinarily skilled individuals, we might consider remote work options